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LT1671 Datasheet(PDF) 3 Page - Linear Technology |
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LT1671 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 12 page  3 LT1671 ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V+ = 5V, V– = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOH Output Voltage Swing High V + ≥ 4.6V, IOUT = 400µA q 2.7 3.1 V V + ≥ 4.6V, IOUT = 4mA q 2.4 3.0 V VOL Output Voltage Swing Low IOUT = – 400µA q 0.3 0.5 V IOUT = – 4mA 0.4 V I+ Positive Supply Current 450 800 µA q 1000 µA I– Negative Supply Current 75 200 µA q 250 µA VIH LATCH Pin High Input Voltage q 2V VIL LATCH Pin Low Input Voltage q 0.8 V IIL LATCH Pin Current VLATCH = 0V q – 1000 – 250 nA tPD1 Propagation Delay ∆VIN = 100mV, VOD = 20mV 60 80 ns q 110 ns tPD2 Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 85 100 ns q 130 ns ∆tPD Differential Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 15 30 ns tLPD Latch Propagation Delay (Note 8) 60 ns tSU Latch Setup Time (Note 8) –15 ns tH Latch Hold Time (Note 8) 35 ns tPW(D) Minimum Disable Pulse Width 30 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It has not been tested. Note 3: The LT1671CS8 and LT1671CMS8 are guaranteed to meet specified performance from 0 °C to 70°C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at – 40 °C and 85°C. The LT1671IS8 is guaranteed to meet the extended temperature limits. Note 4: Input offset voltage (VOS) is defined as the average of the two voltages measured by forcing first one output, then the other to 1.4V. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. Note 7: tPD and ∆tPD cannot be measured in automatic handling equipment with low values of overdrive. The LT1671 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that tPD and ∆tPD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Propagation delay (tPD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: ∆tPD = tPDLH – tPDHL Note 8: Latch propagation delay (tLPD) is the delay time for the output to respond when the LATCH pin is deasserted. Latch setup time (tSU) is the interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable. |
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