M4-128SLASH64-18YI datasheet(10/46 Pages) LATTICE

Part #	M4-128/64-18YI

Description	High Performance E 2 CMOS In-System Programmable Logic

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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10

MACH 4 Family

Macrocell

The macrocell consists of a storage element, routing resources, a clock multiplexer, and

initialization control. The macrocell has two fundamental modes: synchronous and

asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the

macrocell.

In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous

mode will generally be used, since it provides more product terms in the allocator.

SWAP

D/T/L

Q

AP

AR

Power-Up

Reset

PAL-Block

Initialization

Product Terms

From Logic Allocator

Block CLK0

Block CLK1

Block CLK2

Block CLK3

To Output and Input

Switch Matrices

Common PAL-block resource

Individual macrocell resources

From

PAL-Clock

Generator

D/T/L

Q

AP

AR

Power-Up

Reset

Individual

Initialization

Product Term

From Logic

Allocator

Block CLK0

Block CLK1

To Output and Input

Switch Matrices

Individual Clock

Product Term

From PAL-Block

Clock Generator

17466G-010

Figure 5. Macrocell

17466G-009

a. Synchronous mode

b. Asynchronous mode

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M4-128/64-18YI Datasheet(PDF) 10 Page - Lattice Semiconductor

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