3

LT1175

unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as

absolute values except where polarity is not obvious.

GND Pin Current Increase with Load (Note 4)

q

10

20

µA/mA

Input Supply Current in Shutdown

10

20

µA

q

25

µA

Shutdown Thresholds (Note 9)

Either Polarity On SHDN Pin

q

0.8

2.5

V

SHDN Pin Current (Note 2)

q

48

µA

1

4

µA

Output Bleed Current in Shutdown (Note 6)

0.1

1

µA

q

15

µA

SENSE Pin Input Current

(Adjustable Part Only, Current Flows Out of Pin)

q

75

150

nA

(Fixed Voltage Only, Current Flows Out of Pin)

q

12

20

µA

Dropout Voltage (Note 7)

q

0.1

0.2

V

q

0.18

0.26

V

q

0.5

0.7

V

q

0.33

0.5

V

q

0.3

0.45

V

q

0.26

0.45

V

Current Limit (Note 11)

q

520

800

1300

mA

q

390

600

975

mA

q

260

400

650

mA

q

130

200

325

mA

Line Regulation (Note 10)

q

0.003

0.015

%/V

Load Regulation (Note 5, 10)

q

0.1

0.35

%

Thermal Regulation

5-Pin Packages

0.04

0.1

%/W

8-Pin Packages

0.1

0.2

%/W

Output Voltage Temperature Drift

0.25

1.25

%

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Note 8: Thermal regulation is a change in the output voltage caused by die

temperature gradients, so it is proportional to chip power dissipation.

Temperature gradients reach final value in less than 100ms. Output

voltage changes after 100ms are due to absolute die temperature changes

and reference voltage temperature coefficient.

Note 9: The lower limit of 0.8V is guaranteed to keep the regulator in

shutdown. The upper limit of 2.5V is guaranteed to keep the regulator

active. Either polarity may be used, referenced to GND pin.

Note 10: Load and line regulation are measured on a pulse basis with

pulse width of 20ms or less to keep chip temperature constant. DC

regulation will be affected by thermal regulation (Note 8) and chip

temperature changes. Load regulation specification also holds for currents

Note 11: Current limit is reduced for input-to-output voltage above 12V.

See the graph in Typical Performance Characteristics for guaranteed limits

above 12V.

Note 12: Operating at very large input-to-output differential voltages

(>15V) with load currents less than 5mA requires an output capacitor with

an ESR greater than 1

Ω to prevent low level output oscillations.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: SHDN pin maximum positive voltage is 30V with respect to

power level holds only for input-to-output voltages up to 12V, beyond

which internal power limiting may reduce power. See Guaranteed Current

Limit curve in Typical Performance Characteristics section. Note that all

conditions must be met.

Note 4: GND pin current increases because of power transistor base drive.

At low input-to-output voltages (< 1V) where the power transistor is in

saturation, GND pin current will be slightly higher. See Typical

Performance Characteristics.

increase higher than the 10

µA to 25µA drawn by the output divider or fixed

voltage SENSE pin, causing the output to rise above the regulated value.

To prevent this condition, an internal active pull-up will automatically turn

on, but supply current will increase.

Note 6: This is the current required to pull the output voltage to within 1V

of ground during shutdown.

Note 7: Dropout voltage is measured by setting the input voltage equal to

the normal regulated output voltage and measuring the difference between