PALCE22V10Z-25SI datasheet(3/34 Pages) LATTICE

Part #	PALCE22V10Z-25SI

Description	24-Pin EE CMOS (Zero Power) Versatile PAL Device

Download	34 Pages

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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PALCE22V10 and PALCE22V10Z Families

3

Variable Input/Output Pin Ratio

The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.

Buffers for device inputs have complementary outputs to provide user-programmable input signal

polarity. Unused input pins should be tied to VCC or GND.

Registered Output Conﬁguration

Each macrocell of the PALCE22V10 includes a D-type ﬂip-ﬂop for data storage and

synchronization. The ﬂip-ﬂop is loaded on the LOW-to-HIGH transition of the clock input. In the

registered conﬁguration (S1 = 0), the array feedback is from Q of the ﬂip-ﬂop.

Combinatorial I/O Conﬁguration

Any macrocell can be conﬁgured as combinatorial by selecting the multiplexer path that bypasses

the ﬂip-ﬂop (S1 = 1). In the combinatorial conﬁguration, the feedback is from the pin.

0 = Programmed EE bit

1 = Erased (charged) EE bit

Figure 1. Output Logic Macrocell Diagram

16564E-004

CLK

S1

10

11

00

01

AR

SP

0

1

I/On

S0

D Q

Q

S1

S0

Output Conﬁguration

0

Registered/Active Low

0

1

Registered/Active High

1

0

Combinatorial/Active Low

1

Combinatorial/Active High

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PALCE22V10Z-25SI Datasheet(PDF) 3 Page - Lattice Semiconductor

PALCE22V10Z-25SI Datasheet(HTML) 3 Page - Lattice Semiconductor

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