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PALLV22V10 and PALLV22V10Z Families

Quality and Testability

The PALLV22V10 offers a very high level of built-in quality. The erasability of the CMOS

PALLV22V10 allows direct testing of the device array to guarantee 100% programming and

functional yields.

Technology

The high-speed PALLV22V10 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS

process. The array connections are formed with proven EE cells. Inputs and outputs are designed

to be 3.3-V and 5-V device compatible. This technology provides strong input-clamp diodes,

output slew-rate control, and a grounded substrate for clean switching.

Zero-Standby Power Mode

The PALLV22V10Z features a zero-standby power mode. When none of the inputs switch for an

extended period (typically 30 ns), the PALLV22V10Z will go into standby mode, shutting down

maintain the states held before the device went into the standby mode.

standby mode status for that macrocell.

current. The use of combinatorial macrocells will add on average 5 mA per macrocell (at 25 MHz)

under these same conditions.

When any input switches, the internal circuitry is fully enabled, and power consumption returns

to normal. This feature results in considerable power savings for operation at low to medium

frequencies.

Product-Term Disable

On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut

off from these product terms so that they do not draw current. Product-term disabling results in

considerable power savings. This saving is greater at the higher frequencies.

Further hints on minimizing power consumption can be found in a separate document entitled,

Minimizing Power Consumption with Zero-Power PLDs.