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UPD72871FA2 Datasheet(PDF) 35 Page - NEC |
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UPD72871FA2 Datasheet(HTML) 35 Page - NEC |
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35 / 48 page  Preliminary Data Sheet S13925EJ2V0DS00 35 µµµµPD72870,72871 4.1.2 Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded, converted from parallel to serial and transmitted. While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel after synchronization by SCLK Note, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of 100/200/400 Mbps. The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of the 1394 bus is transmitted to the state machine in the LSI. Note The SCLK is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the µPD72870,72871. 4.1.3 CPS An external resistance of 390 k Ω is connected in series to the power cable to monitor the power of the power cable. If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed. 4.1.4 Unused Ports TpAp, TpAn : Not connected TpBp, TpBn : AGND TpBias : Connected to AGND using a 1.0 µF load capacitor 4.2 PLL and Crystal Oscillation Circuit 4.2.1 Crystal Oscillation Circuit To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm. 4.2.2 PLL The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz). 4.3 PC0-PC2, CMC CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit in the PHY register when the input is High. The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Power- on Reset. Use a pull-up or pull-down resistor of 10 k Ω, based on the device’s specification. The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up or pull-down resistor of 10 k Ω based on the application. 4.4 P_RESETB Connect an external capacitor of 0.1 µF between the pins P_RESETB and GND. If the voltage drops below 0 V, a reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register. 4.5 RI0, RI1 Connect an external resistor of 9.1 k Ω to limit the LSI’s current. 5 5 5 5 |
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Similar Description - UPD72871FA2 |
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