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PALCE22V10 Datasheet(PDF) 2 Page - Lattice Semiconductor

Part No. PALCE22V10
Description  24-Pin EE CMOS (Zero Power) Versatile PAL Device
Download  34 Pages
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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PALCE22V10 Datasheet(HTML) 2 Page - Lattice Semiconductor

 
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PALCE22V10 and PALCE22V10Z Families
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming
EE cells to configure AND and OR gates within the device, according to the desired logic function.
Complex interconnections between gates, which previously required time-consuming layout, are
lifted from the PC board and placed on silicon, where they can be easily modified during
prototyping or production.
The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features
of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product
term disable.
Product terms with all connections opened assume the logical HIGH state; product terms
connected to both true and complement of any single input assume the logical LOW state.
The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output configurations registered output or combinatorial I/O, active high or active low
(see Figure 1). The configuration choice is made according to the user’s design specification and
corresponding programming of the configuration bits S0 - S1. Multiplexer controls are connected
to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing
the bit disconnects the control line from GND and it is driven to a high level, selecting the “1” path.
The device is produced with an EE cell link at each input to the AND gate array, and connections
may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-
implemented programming algorithm, these products can be rapidly programmed to any
customized pattern.
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
RESET
PRESET
CLK/I0
1
I1 - I11
11
8
1012
14
16
1614
12
10
8
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
PROGRAMMABLE
AND ARRAY
(44 x 132)


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