MACHLV210-12 datasheet(25/29 Pages) LATTICE

Part #	MACHLV210-12

Description	High Density EE CMOS Programmable Logic

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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25 / 29 page

25

MACHLV210-12/15/20

SWITCHING WAVEFORMS

tWICH

Clock

Input Register Clock Width

(MACH 2 and 4)

VT

tWICL

VT

tARW

VT

tAR

Asynchronous Reset

Input, I/O, or

Feedback

Registered

Output

Clock

tARR

Asynchronous Preset

Registered

Output

Clock

VT

Outputs

Output Disable/Enable

tER

tEA

VOH

- 0.5V

VOL

+ 0.5V

Notes:

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

Input, I/O,

or Feedback

VT

Input, I/O, or

Feedback

tAPW

VT

tAP

tAPR

Input

Latch

Gate

Input Latch Gate Width

(MACH 2 and 4)

tWIGL

VT

17908D-19

17908D-20

17908D-21

17908D-22

17908D-23

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MACHLV210-12 Datasheet(PDF) 25 Page - Lattice Semiconductor

MACHLV210-12 Datasheet(HTML) 25 Page - Lattice Semiconductor

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