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MACHLV210-12 Datasheet(PDF) 4 Page - Lattice Semiconductor

Part No. MACHLV210-12
Description  High Density EE CMOS Programmable Logic
Download  29 Pages
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

MACHLV210-12 Datasheet(HTML) 4 Page - Lattice Semiconductor

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MACHLV210-12/15/20 (Com’l)
ORDERING INFORMATION
Commercial Products
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local
sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
OPERATING CONDITIONS
C = Commercial (0
°C to +70°C)
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
SPEED
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
MACHLV210-12
MACHLV210-15
MACHLV210-20
MACH
-12
J
C
Valid Combinations
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
210
DEVICE NUMBER
210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down
Resistors
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
JC
LV
TECHNOLOGY
LV = Low Voltage


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