2

Specifications ispGDX Family

Description (Continued)

ing Pool (GRP). All I/O pin inputs enter the GRP directly

or are registered or latched so they can be routed to the

required I/O outputs. I/O pin inputs are defined as four

sets (A,B,C,D) which have access to the four MUX inputs

found in each I/O cell. Each output has individual, pro-

grammable I/O tri-state control (OE), output latch clock

(CLK) and two multiplexer control (MUX0 and MUX1)

inputs. Polarity for these signals is programmable for

each I/O cell. The MUX0 and MUX1 inputs control a fast

4:1 MUX, allowing dynamic selection of up to four signal

sources for a given output. OE, CLK and MUX0 and

MUX1 inputs can be driven directly from selected sets of

I/O pins. Optional dedicated clock input pins give mini-

mum clock-to-output delays.

Through in-system programming, connections between

I/O pins and architectural features (latched or registered

inputs or outputs, output enable control, etc.) can be

defined. In keeping with its data path application focus,

the ispGDX devices contain no programmable logic

arrays. All input pins include Schmitt trigger buffers for

noise immunity. These connections are programmed

Non-volatile technology means the device configuration

is saved even when the power is removed from the

device.

In addition, there are no pin-to-pin routing constraints for

1:1 or 1:n signal routing. That is,

any I/O pin configured

as an input can drive one or more I/O pins configured as

outputs.

The device pins also have the ability to set outputs to

fixed HIGH or LOW logic levels (Jumper or DIP Switch

mode). Device outputs are specified for 24mA sink and

source current and can be tied together in parallel for

greater drive. Programmable output slew rate can be

defined independently for each I/O pin to reduce overall

ground bounce and switching noise.

All I/O pins are equipped with IEEE1149.1-compliant

Boundary Scan Test circuitry for enhanced testability. In

addition, in-system programming is supported through

the Test Access Port via a special set of private com-

mands or through Lattice’s industry-standard ISP protocol.

The BSCAN/

ispEN pin is used to make this selection.

The ispGDX I/Os are designed to withstand “live inser-

tion” system environments. The I/O buffers are disabled

during power-up and power-down cycles. When design-

ing for “live insertion,” absolute maximum rating conditions

for the Vcc and I/O pins must still be met. For additional

information, an application note about using Lattice de-

vices in hot swap environments can be downloaded from

the Lattice web site at www.latticesemi.com.

Table 1. ispGDX Family Members

ispGDX DEVICE

ispGDX80A

ispGDX120A

ispGDX160/A

I/O Pins

80

120

160

I/O-OE Inputs*

20

30

40

I/O-Clk Inputs*

20

30

40

I/O-MUXsel1 Inputs*

20

30

40

I/O-MUXsel2 Inputs*

20

30

40

BSCAN / ISP Interface

4

4

4

RESET

11

1

Power/GND

12

25

33

Pin Count/Package

100-Pin TQFP

176-Pin TQFP/

160-Pin PQFP

208-Pin PQFP

272-Ball BGA

* The CLK, OE, MUX0 and MUX1 terminals on each I/O cell can each access 25% of the I/Os.

** MUXed with Y1.

TOE

1**

1

1

Dedicated Clock Pins

2

4

4

BSCAN /

ispEN

11

1