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GAL6002 Datasheet(PDF) 1 Page - Lattice Semiconductor |
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GAL6002 Datasheet(HTML) 1 Page - Lattice Semiconductor |
1 / 16 page ![]() GAL6002 High Performance E2CMOS FPLA Generic Array Logic™ 1 ILMC INPUT LOGIC MACROCELL IOLMC I/O LOGIC MACROCELL BLMC BURIED LOGIC MACROCELL OLMC OUTPUT LOGIC MACROCELL 1 12 13 24 I/ICLK I I I I I I I I I I GND Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q OCLK I/O/Q I/O/Q 6 18 228 I I I I I I NC NC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q 4 5 7 9 11 12 14 16 18 19 21 23 25 26 GAL6002 Top View PLCC DIP GAL 6002 OUTPUT ENABLE AND OR D 11 2 INPUT CLOCK ICLK 14 23 IOLMC ILMC OLMC E OUTPUTS 14 - 23 14 23 0 7 BLMC D E OUTPUT CLOCK OCLK { INPUTS 2-11 { Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 6002_02 Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs — UltraMOS® Advanced CMOS Technology • ACTIVE PULL-UPS ON ALL PINS • LOW POWER CMOS — 90mA Typical Icc • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • UNPRECEDENTED FUNCTIONAL DENSITY — 78 x 64 x 36 FPLA Architecture — 10 Output Logic Macrocells — 8 Buried Logic Macrocells — 20 Input and I/O Logic Macrocells • HIGH-LEVEL DESIGN FLEXIBILITY — Asynchronous or Synchronous Clocking — Separate State Register and Input Clock Pins — Functional Superset of Existing 24-pin PAL® and FPLA Devices • APPLICATIONS INCLUDE: — Sequencers — State Machine Control — Multiple PLD Device Integration Description Having an FPLA architecture, the GAL6002 provides superior flexibility in state-machine design. The GAL6002 offers the highest degree of functional integration, flexibility, and speed currently available in a 24-pin, 300-mil package. E2CMOS technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. The GAL6002 has 10 programmable Output Logic Macrocells (OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In addition, there are 10 Input Logic Macrocells (ILMC) and 10 I/O Logic Macrocells (IOLMC). Two clock inputs are provided for independent control of the input and output macrocells. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Pin Configuration Macrocell Names PinNames I 0 - I10 INPUT I/O/Q BIDIRECTIONAL ICLK INPUT CLOCK V CC POWER (+5V) OCLK OUTPUT CLOCK GND GROUND Functional Block Diagram |