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GAL6001 Datasheet(PDF) 3 Page - Lattice Semiconductor

Part No. GAL6001
Description  High Performance E2CMOS FPLA Generic Array Logic
Download  15 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

GAL6001 Datasheet(HTML) 3 Page - Lattice Semiconductor

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Specifications GAL6001
3
The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin 1
(ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Configurable input blocks
provide system designers with unparalleled design flexibility. With
the GAL6001, external registers and latches are not necessary.
Both the ILMC and the IOLMC are block configurable. However,
the ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations are shown in the macrocell equivalent
diagrams on the following pages.
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND ar-
ray, are available at the device pins. Cells in this group are known
as Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the “D” XOR.
Polarity selection is available for BLMCs, since both the true and
complemented forms of their outputs are available in the AND array.
Polarity of all “E” sum terms is selected through the “E” XOR.
When the macrocell is configured as a D/E type register, it is clocked
from the common OCLK and the register clock enable input is con-
trolled by the associated “E” sum term. This configuration is useful
for building counters and state-machines with state hold functions.
When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its “E” sum term is
routed directly to the clock input. This permits asynchronous pro-
grammable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are reset
to a logic zero. If connected to an output pin, a logic one will oc-
cur because of the inverting output buffer.
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer and always present). When the OLMC is used as an out-
put, the second feedback path is through the IOLMC. With this dual
feedback arrangement, the OLMC can be permanently buried (the
associated OLMC pin is an input), or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS-, JK-, and T-type registers with the same efficiency as a dedi-
cated RS-, JK-, or T-register.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)


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