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AN4660 Datasheet(PDF) 11 Page - STMicroelectronics |
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AN4660 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 27 page DocID027558 Rev 2 11/27 AN4660 Peripheral migration 26 2.3 Flash memory Table 7 presents the differences between the Flash memory interface of STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. The STM32F74xxx/F75xxx devices instantiate a different Flash module both in terms of architecture and interface. For more information on programming, erasing and protection of the STM32F74xxx/F75xxx Flash memory, please refer to the STM32F74xxx and STM32F75xxx reference manual (RM0385). Table 7. Flash memory differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx Flash STM32F42xxx/F43xxx STM32F74xxx/F75xxx Main/program memory 0x0800 0000 – 0x081F FFFF 0x0800 0000 - 0x080F FFFF (on AXIM interface) – Up to 2 Mbyte – Split in 2 Banks – 4 sectors of 16 Kbyte – 1 sector of 64 Kbyte – 6 sectors of 128 Kbyte – Up to 1 Mbyte – Split in 1 Bank – 4 sectors of 32 Kbyte – 1 sector of 128 Kbyte – 3 sectors of 256 Kbyte Features – 128 bit wide data read – Read while Write (RWW) – 256 bit wide data read Wait State Up to 8 (depending on the supply voltage and frequency) Up to 9 (depending on the supply voltage and frequency) One time programmable (OTP) 512 OTP bytes 1024 OTP bytes Flash interface register 0x4002 3C00 - 0x4002 3FFF Option Bytes Base address 0x1FFF C000 - 0x1FFF C00F 0x1FFE C000 - 0x1FFE C00F 0x1FFF 0000 - 0x1FFF 001F (on AXIM interface) Option Bytes FLASH_ OPTCR register – Bit 31 SPRMOD – Bit 30 DB1M – Bits 29:28 Reserved – Bits 27:16 nWRP[11:0] – Bits 15:8 RDP –Bits 7:5 USER - Bit 7: nRST_STDBY - Bit 6: nRST_STOP - Bit 5: WDG_SW – Bit 4 BFB2 – Bits 3:2 BOR_LEV –Bit 1 OPTSTRT – Bit 0 OPTLOCK – Bit 31 IWDG_STOP – Bit 30 IWDG_STDBY – Bits 29:24 Reserved – Bits 23:16 nWRP[7:0] – Bits 15:8 RDP[7:0] – Bits 7:4 USER - Bit 7: nRST_STDBY - Bit 6: nRST_STOP - Bit 5: IWDG_SW – Bit 4: WWDG_SW – Bits 3:2 BOR_LEV[1:0] – Bit 1 OPTSTRT – Bit 0 OPTLOCK |
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