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GAL20LV8 Datasheet(PDF) 3 Page - Lattice Semiconductor

Part No. GAL20LV8
Description  Low Voltage E2CMOS PLD Generic Array Logic
Download  17 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

GAL20LV8 Datasheet(HTML) 3 Page - Lattice Semiconductor

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Specifications GAL20LV8
3
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL20LV8D . The
information given on these architecture bits is only to give a bet-
ter understanding of the device. Compiler software will transpar-
ently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL20LV8D
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 2 and pin 16 are permanently configured
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 2 and pin 16 become dedicated inputs and
use the feedback paths of pin 26 and pin 18 respectively. Because
of this feedback path usage, pin 26 and pin 18 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
21 and 23) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Registered
Complex
Simple
Auto Mode Select
ABEL
P20V8R
P20V8C
P20V8AS
P20V8
CUPL
G20V8MS
G20V8MA
G20V8AS
G20V8
LOG/iC
GAL20V8_R
GAL20V8_C7
GAL20V8_C8
GAL20V8
OrCAD-PLD
"Registered"1
"Complex"1
"Simple"1
GAL20V8A
PLDesigner
P20V8R2
P20V8C2
P20V8C2
P20V8A
TANGO-PLD
G20V8R
G20V8C
G20V8AS3
G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
PAL Architectures
GAL20LV8D
Emulated by GAL20LV8D
Global OLMC Mode
20R8
Registered
20R6
Registered
20R4
Registered
20RP8
Registered
20RP6
Registered
20RP4
Registered
20L8
Complex
20H8
Complex
20P8
Complex
14L8
Simple
16L6
Simple
18L4
Simple
20L2
Simple
14H8
Simple
16H6
Simple
18H4
Simple
20H2
Simple
14P8
Simple
16P6
Simple
18P4
Simple
20P2
Simple
Output Logic Macrocell (OLMC)
Compiler Support for OLMC


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