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LTC4304 Datasheet(PDF) 8 Page - Linear Technology

Part No. LTC4304
Description  Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC4304 Datasheet(HTML) 8 Page - Linear Technology

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LTC4304
8
4304fa
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 1 for a VCC
= 3.3V and a 10k pull-up resistor on each side (50pF on
one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective tPLH is negative.
There is a propagation delay, tPHL, through the connec-
tion circuitry for falling waveforms. Figure 2 shows the
falling edge waveforms. An external driver pulls down
the voltage on the side with 50pF capacitance; LTC4304
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows tPHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. Larger output capacitances translate to longer
delays. Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their systems
and adjust setup and hold times accordingly.
READY Digital Output
The READY pin provides a digital flag which indicates the
status of the connection circuitry described previously in
the “Connection Circuitry” section. READY is high when
the connection circuitry is active, and pulls low when
there is not a valid connection. The pin is driven by an
open drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor of 10k to VCC to
provide the pull-up.
FAULT Digital Output
The FAULT pin provides a digital flag which is low when
SDAOUT and SCLOUT have not both been high within 30ms
(typical). The pin is driven by an open drain pull-down
capable of sinking 3mA while holding 0.4V on the pin.
Connect a resistor of 10k to VCC to provide the pull-up.
ENABLE
When the ENABLE pin is driven below 0.8V with respect
to the LTC4304’s ground, the backplane side is discon-
nected from the card side, and the READY pin is internally
pulled low. When the pin is driven above 2V, the part
waits for data transactions on both the backplane and
card sides to be complete (as described in the Start-Up
section) before connecting the two sides. At this time the
internal pulldown on READY releases. When ENABLE is
low, automatic clocking is disabled.
Figure 1. Input-Output Connection tPLH
Figure 2. Input-Output Connection tPHL
OUTPUT SIDE
50pF
0.5V/DIV
INPUT SIDE
150pF
0.5V/DIV
200ns/DIV
4303 F01
INPUT SIDE
50pF
0.5V/DIV
OUTPUT SIDE
150pF
0.5V/DIV
20ns/DIV
4303 F02
OPERATION


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