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ISPLSI5512VA-100LB388 Datasheet(PDF) 9 Page - Lattice Semiconductor

Part # ISPLSI5512VA-100LB388
Description  In-System Programmable 3.3V SuperWIDE??High Density PLD
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPLSI5512VA-100LB388 Datasheet(HTML) 9 Page - Lattice Semiconductor

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Specifications ispLSI 5512VA
9
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
TCK
TDO
Data to be
captured
Data to be
driven out
Valid Data
Valid Data
Valid Data
Valid Data
Data Captured
btsu
T
bth
T
btcl
T
btch
T
btcp
T
btvo
T
btco
T
btoz
T
btcpsu
T
btcph
T
btuov
T
btuco
T
btuoz
T
SYMBOL
PARAMETER
MIN
MAX
UNITS
tbtcp
TCK [BSCAN test] clock pulse width
125
–
ns
tbtch
TCK [BSCAN test] pulse width high
62.5
–
ns
tbtcl
TCK [BSCAN test] pulse width low
62.5
–
ns
tbtsu
TCK [BSCAN test] setup time
25
–
ns
tbth
TCK [BSCAN test] hold time
25
–
ns
trf
TCK [BSCAN test] rise and fall time
50
–
mV/ns
tbtco
TAP controller falling edge of clock to valid output
–
25
ns
tbtoz
TAP controller falling edge of clock to data output disable
–
25
ns
tbtvo
TAP controller falling edge of clock to data output enable
–
25
ns
tbtcpsu
BSCAN test Capture register setup time
25
–
ns
tbtcph
BSCAN test Capture register hold time
25
–
ns
tbtuco
BSCAN test Update reg, falling edge of clock to valid output
–
50
ns
tbtuoz
BSCAN test Update reg, falling edge of clock to output disable
–
50
ns
tbtuov
BSCAN test Update reg, falling edge of clock to output enable
–
50
ns


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