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GAL16V811111 Datasheet(PDF) 4 Page - Lattice Semiconductor

Part No. GAL16V811111
Description  High Performance E2CMOS PLD Generic Array Logic
Download  23 Pages
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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GAL16V811111 Datasheet(HTML) 4 Page - Lattice Semiconductor

 
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Specifications GAL16V8
1996 Data Book
3-68
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.
Registered outputs have eight product terms per output. I/O's
have seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
DQ
Q
CLK
OE
XOR
XOR


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