ISPLSI5384VA-100LB272 datasheet(7/28 Pages) LATTICE

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ISPLSI5384VA-100LB272 Datasheet(PDF) 7 Page - Lattice Semiconductor

Part #	ISPLSI5384VA-100LB272

Description	In-System Programmable 3.3V SuperWIDE??High Density PLD

Download	28 Pages

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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7 / 28 page

Specifications ispLSI 5384VA

Global Clock Distribution

The ispLSI 5000V Family has four dedicated clock input

pins: CLK0 - CLK3. CLK0 input is used as the dedicated

master clock that has the lowest internal clock skew with

no clock inversion to maintain the fastest internal clock

speed. The clock inversion is available on the remaining

CLK1 - CLK3 signals. By sharing the pins with the I/O

pins, CLK2 and CLK3 can not only be inverted but also is

available for logic implementation through GRP signal

routing. Figure 5 shows these different clock distribution

options.

Figure 5. ispLSI 5000V Global Clock Structure

CLK0

CLK1

CLK 0

CLK 1

IO/CLK 2

IO/CLK 3

CLK2

CLK3

To GRP

SET/RESET

GSET/GRST

Manufacturer	Part #	Datasheet	Description
Lattice Semiconductor	ISPLSI5384VA-100LB272	311Kb / 31P	In-System Programmable 3.3V SuperWIDE??High Density PLD

Manufacturer	Part #	Datasheet	Description
Lattice Semiconductor	ISPLSI5256VE	246Kb / 24P	In-System Programmable 3.3V SuperWIDE High Density PLD
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	ISPLSI5384VE-125LB272	242Kb / 22P	In-System Programmable 3.3V SuperWIDE??High Density PLD
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	5384VA	311Kb / 31P	In-System Programmable 3.3V SuperWIDE??High Density PLD
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	2064VE	200Kb / 15P	3.3V In-System Programmable High Density SuperFAST??PLD

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