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ISPLSI2064VL-135LT100I Datasheet(PDF) 7 Page - Lattice Semiconductor |
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ISPLSI2064VL-135LT100I Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 14 page 7 Specifications ispLSI 2064VL ispLSI 2064VL Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs I/O Pin (Input) Y0,1,2 GRP GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Delay I/O Cell ORP GLB GRP I/O Cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 Reset Ded. In #21 #20 #28 #29, 30, 31, 32 #38, 39 GOE 0,1 #42 #40, 41 0491/2064VL #22 Comb 4 PT Bypass #23 #37 #45 Derivations of tsu, th and tco from the Product Term Clock = = = = tsu Logic + Reg su - Clock (min) ( tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 1.1 + 3.4) + (1.2) - (0.5 + 1.1 + 1.1) = = = = th Clock (max) + Reg h - Logic ( tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 1.1 + 4.1) + (2.3) - (0.5 + 1.1 + 3.4) = = = = tco Clock (max) + Reg co + Output ( tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 1.1 + 4.1) + (0.3) + (1.4 + 1.6) Table 2-0042/2064VL Note: Calculations are based on timing specifications for the ispLSI 2064VL-165L. 3.5ns 3.0ns 9.0ns |
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