9

Specifications ispLSI and pLSI 1032E

1. Internal Timing Parameters are not tested and are for reference only.

Table 2-0037A/1032E

Outputs

UNITS

-100

MIN.

MIN.

MAX.

MAX.

DESCRIPTION

#

PARAM.

49 Output Buffer Delay

ns

51 I/O Cell OE to Output Enabled

ns

54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)

ns

Global Reset

Clocks

59 Global Reset to GLB and I/O Registers

ns

52 I/O Cell OE to Output Disabled

ns

55 Clk Delay, Y1 or Y2 to Global GLB Clk Line

ns

56 Clk Delay, Clock GLB to Global GLB Clk Line

ns

57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line

ns

58 Clk Delay, Clk GLB to I/O Cell Global Clk Line

ns

53 Global OE

ns

50 Output Buffer Delay, Slew Limited Adder

ns

-125

–

–

1.5

–

1.5

0.8

0.0

0.8

–

–

–

2.0

5.1

1.5

4.3

5.1

1.5

1.8

0.0

1.8

3.9

10.0

–

–

1.4

–

1.4

0.8

0.0

0.8

–

–

–

1.3

4.3

1.4

2.8

4.3

1.4

1.8

0.0

1.8

2.7

9.9