Data Sheet S14265EJ2V0DS00

15

2.1.11 Offset_10

Base Address 0 Register

This register specifies the base memory address for accessing all the “Operation registers” (i.e. control,

configuration, and status registers) of the

µPD72862, while the BIOS is expected to set this value during power-up

reset.

Bits

R/W

Description

11-0

R

Constant value of 000H. These bits are “read-only”.

31-12

R/W

-

2.1.12 Offset_2C

Subsystem Vendor ID Register

This register identifies the subsystem that contains the NEC’s

µPD72862 function. While the ID is assigned by the

PCI_SIG committee, the value should be loaded into the register from the external serial EEPROM after power-up

reset. Access to this register through PCI-bus is prohibited.

Bits

R/W

Description

15-0

R

Default value of 1033H.

2.1.13 Offset_2E

Subsystem ID Register

This register identifies the type of the subsystem that contains the NEC’s

µPD72862 function. While the ID is

assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after

power-up reset. Access to this register through PCI-bus is prohibited.

Bits

R/W

Description

15-0

R

Default value of 0063H.

2.1.14 Offset_30

Expansion Rom Base Address Register

This register is not supported by the current implementation of the

µPD72862.

Bits

R/W

Description

31-0

R

Reserved Constant value of 0.

2.1.15 Offset_34

Cap_Ptr Register

This register points to a linked list of additional capabilities specific to the

µPD72862, the NEC’s implementation of

the 1394 OpenHCI specification.

Bits

R/W

Description

7-0

R

Constant value of 60H. The value represents an offset into the

µPD72862’s PCI Configuration

Space for the location of the first item in the New Capabilities Linked List.