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ISPLSI2032VE-135LJ44 Datasheet(PDF) 8 Page - Lattice Semiconductor

Part No. ISPLSI2032VE-135LJ44
Description  3.3V In-System Programmable High Density SuperFAST??PLD
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPLSI2032VE-135LJ44 Datasheet(HTML) 8 Page - Lattice Semiconductor

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Specifications ispLSI 2032VE
8
Internal Timing Parameters1
Over Recommended Operating Conditions
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032VE
Inputs
UNITS
-135
MIN.
-110
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
––
1.3
ns
tdin
21 Dedicated Input Delay
––
2.5
ns
tgrp
22 GRP Delay
––
1.2
ns
GLB
t1ptxor
25 1 Product Term/XOR Path Delay
––
5.4
ns
t20ptxor
26 20 Product Term/XOR Path Delay
––
5.4
ns
txoradj
27 XOR Adjacent Path Delay
––
5.4
ns
tgbp
28 GLB Register Bypass Delay
––
1.4
ns
tgsu
29 GLB Register Setup Time before Clock
1.4
ns
tgh
30 GLB Register Hold Time after Clock
4.1
ns
tgco
31 GLB Register Clock to Output Delay
––
1.0
ns
3
tgro
32 GLB Register Reset to Output Delay
––
2.7
ns
tptre
33 GLB Product Term Reset to Register Delay
––
7.1
ns
tptoe
34 GLB Product Term Output Enable to I/O Cell Delay
––
8.6
ns
tptck
35 GLB Product Term Clock Delay
2.5
4.4
ns
ORP
tob
38 Output Buffer Delay
––
1.8
ns
tsl
39 Output Slew Limited Delay Adder
––
2.0
ns
0.8
1.7
GRP
0.9
t4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial)
––
4.8
ns
t4ptbpr
24 4 Product Term Bypass Path Delay (Registered)
––
3.4
ns
4.4
4.4
4.4
1.0
3.9
2.9
1.1
2.9
0.9
1.8
6.1
6.9
1.7
4.1
torp
36 ORP Delay
––
1.9
ns
torpbp
37 ORP Bypass Delay
––
0.9
ns
1.5
0.5
Outputs
1.4
2.0
toen
40 I/O Cell OE to Output Enabled
––
3.4
ns
todis
41 I/O Cell OE to Output Disabled
––
3.4
ns
3.4
3.4
tgoe
42 Global Output Enable
––
3.6
ns
2.6
tgy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.7
1.8
1.8
ns
tgy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.9
2.0
2.0
ns
Clocks
1.7
1.9
tgr
45 Global Reset to GLB
––
7.1
ns
Global Reset
5.3


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