1

In-System Programmable

Functional Block Diagram

Features

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL

CROSSPOINT FAMILY

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement

— “Any Input to Any Output” Routing

— Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation

— Space-Saving PQFP and BGA Packaging

— Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

— 3.3V Core Power Supply

— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*

— 250MHz Maximum Clock Frequency*

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels (Individually Programmable)*

— Low-Power: 16.5mA Quiescent Icc*

Control Option

— PCI Compatible Drive Capability*

— Schmitt Trigger Inputs for Noise Immunity

— Electrically Erasable and Reprogrammable

• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES

— 3.3V In-System Programmable Using Boundary Scan

Test Access Port (TAP)

— Change Interconnects in Seconds

• FLEXIBLE ARCHITECTURE

— Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control

— Dedicated Clock/Clock Enable Input Pins (four) or

Programmable Clocks/Clock Enables from I/O Pins

(40)

— Single Level 4:1 Dynamic Path Selection (Tpd=3.5ns)

— Programmable Wide-MUX Cascade Feature

Supports up to 16:1 MUX

— Programmable Pull-ups, Bus Hold Latch and Open

Drain on I/O Pins

— Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• DESIGN SUPPORT THROUGH LATTICE’S ispGDX

DEVELOPMENT SOFTWARE

— MS Windows or NT / PC-Based or Sun O/S

— Easy Text-Based Design Entry

— Automatic Signal Routing

— Program up to 100 ISP Devices Concurrently

— Simulator Netlist Generation for Easy Board-Level

Simulation

* “VA” Version Only

Global Routing

Pool

(GRP)

I/O

Cells

I/O Pins B

Boundary

Scan

Control

I/O

Cells

ISP

Control

I/O Pins D

Description

The ispGDXV/VA architecture provides a family of fast,

flexible programmable devices to address a variety of

system-level digital signal routing and interface require-

ments including:

• Multi-Port Multiprocessor Interfaces

• Wide Data and Address Bus Multiplexing

(e.g. 16:1 High-Speed Bus MUX)

• Programmable Control Signal Routing

(e.g. Interrupts, DMAREQs, etc.)

• Board-Level PCB Signal Routing for Prototyping or

Programmable Bus Interfaces

The devices feature fast operation, with input-to-output

signal delays (Tpd) of 3.5ns and clock-to-output delays of

3.5ns.

The architecture of the devices consists of a series of

programmable I/O cells interconnected by a Global Rout-

ing Pool (GRP). All I/O pin inputs enter the GRP directly

or are registered or latched so they can be routed to the

required I/O outputs. I/O pin inputs are defined as four

sets (A,B,C,D) which have access to the four MUX inputs

gdx160va_04

Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein

are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

July 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com