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1024 Datasheet(PDF) 6 Page - Lattice Semiconductor

Part No. 1024
Description  In-System Programmable High Density PLD
Download  12 Pages
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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1024 Datasheet(HTML) 6 Page - Lattice Semiconductor

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Specifications ispLSI 1024/883
6
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.3
1.3
1.3
6.0
4.6
2.7
4.0
4.0
3.3
5.3
2.0
2.7
4.0
5.0
6.0
8.3
8.6
9.3
10.6
12.7
1.3
2.7
3.3
13.3
12.0
9.9
3.3
0.7
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-60
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
tgrp24
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
ORP
torp
torpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 24 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.


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