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UPD72042 Datasheet(PDF) 44 Page - NEC |
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UPD72042 Datasheet(HTML) 44 Page - NEC |
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44 / 92 page  µPD72042 44 Data Sheet S14870EJ1V0DS00 DAR1 Address : 0110B (6H) (DAR1) High-order 4 bits DAR2 0111B (7H) (DAR2) Read/write : Read Broadcast address register When reset : Undefined The DAR1 and DAR2 registers are used to hold a broadcast address (master address) involved when a broadcast reception error occurs. DAR1 and DAR2 are updated each time a broadcast reception error occurs (SLRC of the RCR register is set to 1100). So, ensure that when a broadcast reception error occurs, the contents of DAR1 and DAR2 are read by the microcomputer within the time indicated below. • Maximum allowable DAR1 and DAR2 read time: Approx. 5420 µs (mode 0) Approx. 1490 µs (mode 1) Cautions 1. If the microcomputer cannot read the data in DAR1 and DAR2 within the times indicated above, DAR1 and DAR2 may be updated by the occurrence of another broadcast reception error, and the subsequently updated broadcast address may be read. 2. A broadcast address is stored in DAR1 and DAR2 when DERC (broadcast reception selection) of the CMR register is set to 1. b7 Broadcast address (low-order 4 bits) b4 b3 b0 — DAR1 b7 b0 Broadcast address (high-order 8 bits) DAR2 t IRQ |
Similar Part No. - UPD72042 |
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Similar Description - UPD72042 |
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