4

LTC1864L/LTC1865L

sn18645L 18645Lfs

LTC1864L/LTC1865L

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

3.6

V

Clock Frequency

●

DC

8

MHz

Total Cycle Time

µs

Analog Input Sampling Time (Note 5)

LTC1864L

16

SCK

LTC1865L

14

SCK

Setup Time CONV↓ Before First SCK↑

60

ns

(See Figure 1)

Hold Time SDI After SCK↑

LTC1865L

30

ns

Setup Time SDI Stable Before SCK↑

LTC1865L

30

ns

SCK High Time

45%

SCK Low Time

45%

CONV High Time Between Data

µs

Transfer Cycles

CONV Low Time During Data Transfer

16

SCK

Hold Time CONV Low After Last SCK↑

26

ns

LTC1864L/LTC1865L

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Conversion Time (See Figure 1)

●

3.7

4.66

µs

●

150

kHz

Delay Time, SCK↓ to SDO Data Valid

45

55

ns

●

60

ns

Delay Time, CONV↑ to SDO Hi-Z

●

55

120

ns

Delay Time, CONV↓ to SDO Enabled

●

35

120

ns

Time Output Data Remains

●

515

ns

Valid After SCK↓

SDO Rise Time

25

ns

SDO Fall Time

12

ns

RECO

E DED OPERATI G CO DITIO S

TI I G CHARACTERISTICS

The

The

Conditions, unless otherwise noted.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: Integral nonlinearity is defined as deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 4: Channel leakage current is measured while the part is in sample

mode.

not have to be clocked during this time if the SDO data word is not

desired. In the case of the LTC1865L a minimum of 2 clocks are required

on the SCK input after CONV falls to configure the MUX during this time.