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UPD70732 Datasheet(PDF) 22 Page - NEC |
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UPD70732 Datasheet(HTML) 22 Page - NEC |
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22 / 66 page  22 µPD70732 6. INTERRUPT AND EXCEPTION Interrupts are events that take place independently of the program execution and can be classified into maskable interrupts and a non-maskable interrupt. An exception is an event that takes place depending upon the program execution. There is little difference between the interrupt and exception in terms of flow, but the interrupt takes precedence over the exception. The V810 architecture is provided with the interrupts and exceptions listed in the table below. If an exception, a maskable interrupt or NMI occurs, control is transferred to a handler whose address is determined by the source of the interrupt or exception. The exception source can be checked by examining an exception code stored in the ECR (Exception Code Register). Each handler analyzes the contents of the ECR and performs appropriate exception/interrupt servicing. Table 6-1. Exception Codes Exception and interrupt Classification Exception code Handler address Restore PCNote 1 Reset Interrupt F F F 0 F F F F F F F 0 Note 2 NMI Interrupt F F D 0 F F F F F F D 0 next PCNote 3 Duplexed exception Exception Note 4 F F F F F F D 0 current PC Address trap Exception F F C 0 F F F F F F C 0 current PC Trap instruction (parameter is 0x1n) Exception F F B n F F F F F F B 0 next PC Trap instruction (parameter is 0x0n) Exception F F A n F F F F F F A 0 next PC Invalid instruction code Exception F F 9 0 F F F F F F 9 0 current PC Zero division Exception F F 8 0 F F F F F F 8 0 current PC FIV (floating-point invalid operation) Exception F F 7 0 F F F F F F 6 0 current PC FZD (floating-point zero division) Exception F F 6 8 F F F F F F 6 0 current PC FOV (floating-point overflow) Exception F F 6 4 F F F F F F 6 0 current PC FUD (floating-point underflow)Note 5 Exception F F 6 2 F F F F F F 6 0 current PC FPR (floating-point precision degradation)Note 5 Exception F F 6 1 F F F F F F 6 0 current PC FRO (floating-point reserved operand) Exception F F 6 0 F F F F F F 6 0 current PC INT level n (n = 0 to 15) Interrupt F E n 0 F F F F F E n 0 next PCNote 3 Notes 1. PC to be saved to EIPC or FEPC. 2. EIPC and FEPC are undefined. 3. While an instruction whose execution is aborted by an interrupt (DIV/DIVU, single-precision floating- point data, bit string instruction) is executed, restore PC = current PC. 4. The exception code of the exception that occurs for the first time is stored to the lower 16 bits of the ECR, and that of the second exception is stored in the higher 16 bits. 5. In the V810, the floating-point underflow exception and floating-point precision degradation exception do not occur. 5 |
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