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PD72042B Datasheet(PDF) 32 Page - Renesas Technology Corp

Part No. PD72042B
Description  LSI DEVICE FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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PD72042B Datasheet(HTML) 32 Page - Renesas Technology Corp

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µPD72042B
30
Data Sheet S13990EJ3V0DS
Address
Name
High-order 4 bits
Low-order 4 bits
Note
Reference page
0H
0000
CTR
––
REEN SRST
––
STREQ
A
p. 31
1H
0001
CMR
0
LOCK
BUFC
COMC
C
p. 32
1
0
0
0
0
IRS
MFC
DERC
2H
0010
UAR1
Local station address
Condition code
B
p. 34
(low-order 4 bits)
3H
0011
UAR2
Local station address (high-order 8 bits)
B
p. 34
4H
0100
SAR1
Slave address
0
0
0
0
D
p. 35
(low-order 4 bits)
5H
0101
SAR2
Slave address (high-order 8 bits)
D
p. 35
6H
0110
MCR
Broadcast bits
Number of
Control bits
D
p. 36
arbitrations
7H
0111
––
8H
1000
––
EH
1110
TBF
Number of bytes of transmission data, transmission data
F
p. 38
Table 4-1
µPD72042B Registers
(a) Write registers
(b) Read registers
Address
Name
High-order 4 bits
Low-order 4 bits
Note
Reference page
0H
0000
STR
TFL
TEP
RFL
REP
A
p. 39
1H
0001
FLG
MARQ STRQ SLRE
CEX
RAW
STM
IRQ
A
p. 40
2H
0010
RDR1
Number of bytes of master reception data
A
p. 42
3H
0011
RDR2
Number of bytes of slave reception data or
A
p. 42
broadcast reception data
4H
0100
LOR1
Lock address (low-order 8 bits)
H
p. 43
5H
0101
LOR2
Lock state
Lock address
H
p. 43
(high-order 4 bits)
6H
0110
DAR1
Broadcast address
E
p. 44
(low-order 4 bits)
7H
0111
DAR2
Broadcast address (high-order 8 bits)
E
p. 44
8H
1000
RCR
Return codes (MARC, SLRC)
A
p. 45
EH
1110
RBF
Transmitter address, reception data
G
p. 57
Note
Writable and readable periods of the registers of the
µPD72042B
A: Arbitrary
B: After system reset cancellation
C: While CEX of the FLG register (address 0001) is set to 0
D: While MARQ of the FLG register (address 0001) is set to 0
E: After SLRC of the RCR register (address 1000) is set to 1100 (broadcast reception error)
F: While TFL of the STR register (address 0000) is set to 0
G: While REP of the STR register (address 0000) is set to 0
H: When CEX of the FLG register (address 0001) is set to 0 after LOCK of the CMR register (address 0001)
is set to 1


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