LTC1860/LTC1861

10

18601fa

FUNCTIONAL BLOCK DIAGRAM

TEST CIRCUITS

1860/61 BD

12-BIT

SAMPLING

ADC

BIAS AND

SHUTDOWN

CONVERT

CLK

SERIAL

PORT

12-BITS

(CH0)

(CH1)

VCC

VREF

SDO

GND

CONV (SDI) SCK

PIN NAMES IN

PARENTHESES

REFER TO LTC1861

DATA OUT

DATA IN

+

–

SDO

3k

20pF

TEST POINT

1860 TC01

SDO

1860 TC04

1860 TC03

CONV

SDO

SCK

SDO

1860 TC02

SDO

WAVEFORM 1

(SEE NOTE 1)

90%

10%

SDO

WAVEFORM 2

(SEE NOTE 2)

CONV

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

1860 TC05