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LTC1164-5 Datasheet(PDF) 8 Page - Linear Technology |
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LTC1164-5 Datasheet(HTML) 8 Page - Linear Technology |
8 / 16 page LTC1164-5 8 11645fc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VIN 5V ≤ V+ ≤16V 1k VOUT DIGITAL SUPPLY + GND CLOCK SOURCE 1164-5 F02 + LTC1164-5 0.1 µF 1 µF 10k 10k 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VIN V+ 1k V– VOUT LTC1164-5 DIGITAL SUPPLY + GND CLOCK SOURCE * 1164-5 F01 * OPTIONAL (SEE TEXT) 0.1 µF 0.1 µF Power Supply (Pins 4, 12) The V + (Pin4)andtheV–(Pin12)shouldbebypassedwith a 0.1 µF capacitor to an adequate analog ground. The filter’s power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than 1V/ µs. When V + is applied before V–, and V– can be more positive than ground, a signal diode must be used to clamp V –. Figures 1 and 2 show typical connections for dual and single supply operation. Clock Input (Pin 11) Any TTL or CMOS clock source with a square-wave output and 50% duty cycle ( ±10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be connected to clock’s ground at a single point only. Table 1 shows the clock’s low and high level threshold value for a dual or single supply operation. A pulse generator can be used as a clock source provided the high level ON time is greater than 0.5 µs.Sinewavesare not recommended for clock input frequencies less than 100kHz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time ≤1µs). The clock signal should be routed from the right side of the IC package to avoid coupling into any input or output analog signal path. A 1k resistor between clock source and Pin 11 will slow down the rise and fall times of the clock to further reduce charge coupling, Figures 1 and 2. Table 1. Clock Source High and Low Threshold Levels POWER SUPPLY HIGH LEVEL LOW LEVEL Dual Supply > ±3.4V ≥ V+/3 ≤ 0.5V Dual Supply ≤ ±3.4V ≥ V+/3 ≤ V – + 0.5V Single Supply V + > 6.8V, V – = 0V ≥ V+• 0.65 ≤ 0.5V + 1/2V+ Single Supply V + < 6.8V, V – = 0V ≥ V+/3 ≤ 0.5V Analog Ground (Pins 3, 5) The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the pack- age is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, Pins 3 and 5 should be connected to the analog ground plane. For single supply operation Pins 3 and 5 should be biased at 1/2 supply and they should be bypassed to the analog ground plane with at least a 1 µF capacitor (Figure 2). For single 5V operation at the highest fCLK of 1MHz, Pins 3 and 5 should be biased at 2V. This minimizes passband gain and phase variations (see Typi- cal Performance Characteristics curves: Maximum Pass- band for Single 5V, 50:1; and THD + Noise vs RMS Input for Single 5V, 50:1). PI FU CTIO S Figure 1. Dual Supply Operation for fCLK/fCUTOFF = 100:1 Figure 2. Single Supply Operation for fCLK/fCUTOFF = 100:1 |
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