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LTC2604 Datasheet(PDF) 10 Page - Linear Technology

Part No. LTC2604
Description  Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC2604 Datasheet(HTML) 10 Page - Linear Technology

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LTC2604/LTC2614/LTC2624
10
2604fd
TIMING DIAGRAM
outputs from the DAC during this time. The LTC2604/
LTC2614/LTC2624 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power-On Reset
The LTC2604/LTC2614/LTC2624 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2604-1/
LTC2614-1/LTC2624-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
SDI
SDO
CS/LD
SCK
2604 F01
t2
t8
t10
t5
t7
t6
t1
t3
t4
12
3
23
24
OPERATION
Figure 1
2
15
1
GND
REF LO
REF A
VOUTA
VOUTB
REF B
CS/LD
SCK
VCC
REF D
VOUT D
VOUT C
REF C
SDO
SDI
2604 BD
16
3
4
14
DAC A
DAC D
5
7
6
8
10
12
9
13
DAC B
DAC C
DECODE
CONTROL
LOGIC
32-BIT SHIFT REGISTER
CLR
11
BLOCK DIAGRAM


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