7

LT1513/LT1513-2

sn1513 1513fas

The LT1513 is an IC battery charger chip specifically opti-

mized to use the SEPIC converter topology. A complete

charger schematic is shown in Figure 1. The SEPIC topology

has unique advantages for battery charging. It will operate

with input voltages above, equal to or below the battery

voltage, has no path for battery discharge when turned off,

and eliminates the snubber losses of flyback designs. It also

has a current sense point that is ground referred and need

not be connected directly to the battery. The two inductors

shown are actually just two identical windings on one

inductor core, although two separate inductors can be used.

A current sense voltage is generated with respect to ground

across R3 in Figure 1. The average current through R3 is

always identical to the current delivered to the battery. The

LT1513 current limit loop will servo the voltage across R3

to – 100mV when the battery voltage is below the voltage

limit set by the output divider R1/R2. Constant-current

charging is therefore set at 100mV/R3. R4 and C4 filter the

pin. R1 and R2 form a divider for battery voltage sensing and

set the battery float voltage. The suggested value for R2 is

12.4k. R1 is calculated from:

R

RV

RA

BAT

1

2

1 245

1 245

2 0 3

=

+µ

(– .

)

.( .

)

0.3

µA = typical FB pin bias current

A value of 12.4k for R2 sets divider current at 100

µA. This is

a constant drain on the battery when power to the charger is

off. If this drain is too high, R2 can be increased to 41.2k,

reducing divider current to 30

µA. This introduces an addi-

tional uncorrectable error to the constant voltage float mode

of about

±0.5% as calculated by:

V

Error =

0.15 A(R1)(R2)

1.245(R1+ R2)

BAT

±µ

±0.15µA = expected variation in FB bias current around the

nominal 0.3

µA typical value.

to variations in bias current would be

±0.42%.

A second option is to disconnect the divider when charger

power is off. This can be done with a small NFET as shown in

Figure 3. D2, C6 and R6 form a peak detector to drive the gate

of the FET to about the same as the battery voltage. If power

is turned off, the gate will drop to 0V and the only drain on the

battery will be the reverse leakage of the catch diode D1. See

Diode Selection for a discussion of diode leakage.

LT1513

L1A

L1B

GND

1513 F03

ADAPTER

INPUT

C2

SCHEMATIC SIMPLIFIED FOR CLARITY

D2 = 1N914, 1N4148 OR EQUIVALENT

C6

470pF

R6

470k

R3

R1

R2

D2

D1

C1

+

Figure 3. Eliminating Divider Current

Maximum Input Voltage

Maximum input voltage for the LT1513 is partly determined

by battery voltage. A SEPIC converter has a maximum

switch voltage equal to input voltage plus output voltage.

The LT1513 has a maximum input voltage of 30V and a

maximum switch voltage of 40V, so this limits maximum

Shutdown and Synchronization

The dual function S/S pin provides easy shutdown and

synchronization. It is logic level compatible and can be

pulled high or left floating for normal operation. A logic low

on the S/S pin activates shutdown, reducing input supply

current to 12

µA.Tosynchronizeswitching,drivetheS/Spin

between 600kHz and 800kHz.

Inductor Selection

L1A and L1B are normally just two identical windings on one

core, although two separate inductors can be used. A typical

value is 10

µH, which gives about 0.5A peak-to-peak induc-

tor current. Lower values will give higher ripple current,

which reduces maximum charging current. 5

µHcanbeused

if charging currents are at least 20% lower than the values