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LTC1860L Datasheet(PDF) 9 Page - Linear Technology

Part No. LTC1860L
Description  Power, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC1860L Datasheet(HTML) 9 Page - Linear Technology

 
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9
LTC1860L/LTC1861L
18601Lf
Figure 1. LTC1860L Operating Sequence
Figure 3. LTC1860L with Rail-to-Rail Input Span
Figure 2. LTC1860L Transfer Curve
APPLICATIO S I FOR ATIO
CONV
tCONV
SCK
SDO
12
11
10
9
8
7
6
5
4
3
2
1
B11 B10
B8B6
B4B2
B0*
Hi-Z
1860 F01
Hi-Z
B9
B7
B5
B3
B1
SLEEP MODE
tSMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC
WILL OUTPUT ZEROS INDEFINITELY
DON'T CARE
VIN*
*VIN = IN
+ – IN
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
1860 F02
1
2
3
4
8
7
6
5
VREF
IN+
IN
GND
VCC
SCK
SDO
CONV
LTC1860L
1860 F03
VIN = 0V TO VCC
VCC
1
µF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
LTC1861L OPERATION
Operating Sequence
The LTC1861L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1861L goes into sleep mode. The LTC1861L’s 2-bit
data word is clocked into the SDI input on the rising edge
of SCK after CONV goes low. Additional inputs on the SDI
pin are then ignored until the next CONV cycle. The shift
clock (SCK) synchronizes the data transfer with each bit
being transmitted on the falling SCK edge and captured on
the rising SCK edge in both transmitting and receiving
systems. The data is transmitted and received simulta-
neously (full duplex). After completing the data transfer, if
further SCK clocks are applied with CONV low, SDO will
output zeros indefinitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of Table 1. In single-ended
mode, all input channels are measured with respect to
GND (or AGND). A zero code will occur when the “+”
input minus the “–” input equals zero. Full scale occurs
when the “+” input minus the “–” input equals VREF minus
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1861L SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1861L MSOP package defines the span of the
A/D converter. The LTC1861L MSOP package can operate
with reference voltages from 1V to VCC.


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