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LTC1860L Datasheet(PDF) 8 Page - Linear Technology

Part No. LTC1860L
Description  Power, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC1860L Datasheet(HTML) 8 Page - Linear Technology

 
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8
LTC1860L/LTC1861L
18601Lf
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
Voltage Waveforms for SDO Delay Times, tdDO and thDO
Voltage Waveforms for ten
SDO
3k
20pF
TEST POINT
VCC tdis WAVEFORM 2, ten
tdis WAVEFORM 1
1860 TC01
SCK
SDO
VIL
tdDO
thDO
VOH
VOL
1860 TC02
1860 TC03
CONV
SDO
ten
SDO
tr
tf
1860 TC04
VOH
VOL
TEST CIRCUITS
Voltage Waveforms for tdis
SDO
WAVEFORM 1
(SEE NOTE 1)
VIH
tdis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1860 TC05
LTC1860L OPERATION
Operating Sequence
The LTC1860L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1860L goes into sleep mode drawing only leakage
current. On the falling edge of CONV, the LTC1860L goes
into sample mode and SDO is enabled. SCK synchronizes
the data transfer with each bit being transmitted from SDO
on the falling SCK edge. The receiving system should
capture the data from SDO on the rising edge of SCK. After
completing the data transfer, if further SCK clocks are
applied with CONV low, SDO will output zeros indefinitely.
See Figure 1.
Analog Inputs
The LTC1860L has a unipolar differential analog input. The
converter will measure the voltage between the “IN+” and
“IN” inputs. A zero code will occur when IN+ minus IN
equals zero. Full scale occurs when IN+ minus INequals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and VREF is tied to VCC, a rail-to-rail input span
will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1860L (and
the LTC1861L MSOP package) defines the full-scale range
of the A/D converter. These ADCs can operate with refer-
ence voltages from VCC to 1V.
APPLICATIO S I FOR ATIO


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