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UPD17P709 Datasheet(PDF) 11 Page - NEC |
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UPD17P709 Datasheet(HTML) 11 Page - NEC |
11 / 38 page 11 µPD17P709 VDD1 VDD0 VCOH VCOL EO0 EO1 TEST P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 P2B3 to P2B0 P3C3 to P3C0 Function When reset When the clock is stopped 30 79 31 32 34 35 36 37 38 39 40 43 to 46 47 to 50 Power-on reset When reset When the clock is stopped High-impedance output High-impedance output High-impedance output CE reset Input (P1D3-P1D0) Input (P1D3-P1D0) Held (P1D3-P1D0) Held (P1D3-P1D0) WDT&SP reset WDT&SP reset Power-on reset Held Held When reset When the clock is stopped CE reset WDT&SP reset Input Input Power supply. Apply the same voltage to the VDD1 and VDD0 pins. • When the CPU and peripheral functions are operating: 4.5 to 5.5 V • When only the CPU is operating: 3.5 to 5.5 V • When the clock is stopped: 2.2 to 5.5 V Input for PLL local oscillation (VCO) frequency • VCOH • Active when VHF mode is selected by software. Otherwise, pulled down. • VCOL • Active when HF or MW mode is selected by software. Otherwise, pulled down. Inputs to these pins are to be AC-amplified. Cut, therefore, the DC components in the input signals by using capacitors. Output from the charge pump of the PLL frequency synthesizer. The result of phase comparison between the divided local oscillation fre- quency and reference frequency is output. Test input pin. Be sure to connect it to GND. Output for port 1D and BEEP • P1D3-P1D0 • 4-bit I/O port • Input/output can be specified bit by bit. • BEEP1, BEEP0 • BEEP output 4-bit I/O port. Input/output can be specified bit by bit. 4-bit I/O port. Input/output can be specified in 4-bit units. Power-on reset WDT&SP reset CE reset Held Held When reset When the clock is stopped Input Input — — CMOS tristate — CMOS push-pull CMOS push-pull CMOS push-pull Symbol Pin No. Output format Power-on reset High-impedance output CE reset |
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