23

µPD17P709

Fig. 2-1

PA17P709GC and PA-17KDZ

2.1

OPERATING MODES FOR PROGRAM MEMORY WRITE, READ, AND VERIFICATION

The

In this mode, one of the operating modes indicated in Table 2-2 is set, depending on the setting of the MD0 to

MD3 pins.

The input pins that are not used for program memory write, read, and verification are connected to GND through

a pull-down resistor (470 ohms). (See PIN CONFIGURATION, (2) PROM programming mode.)

Table 2-2

Operating Modes for Program Memory Write, Read, and Verication

Remark X: L or H

Operating mode specification

MD0

H

L

L

H

Operating mode

MD2

H

H

H

H

MD1

L

H

L

X

MD3

L

H

H

H

Program memory address zero-clear mode

Write mode

Read/verify mode

Program inhibit mode

+12.5V

+6V

PA-17KDZ

PA-17P709GC

To PG-1500