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UPD17P709 Datasheet(PDF) 23 Page - NEC |
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UPD17P709 Datasheet(HTML) 23 Page - NEC |
23 / 38 page 23 µPD17P709 Fig. 2-1 PA17P709GC and PA-17KDZ 2.1 OPERATING MODES FOR PROGRAM MEMORY WRITE, READ, AND VERIFICATION The µPD17P709 is placed in program memory write, read, and verify mode when +6 V is applied to the VDD pin, and +12.5 V to the VPP pin. In this mode, one of the operating modes indicated in Table 2-2 is set, depending on the setting of the MD0 to MD3 pins. The input pins that are not used for program memory write, read, and verification are connected to GND through a pull-down resistor (470 ohms). (See PIN CONFIGURATION, (2) PROM programming mode.) Table 2-2 Operating Modes for Program Memory Write, Read, and Verication Remark X: L or H Operating mode specification MD0 H L L H VDD VPP Operating mode MD2 H H H H MD1 L H L X MD3 L H H H Program memory address zero-clear mode Write mode Read/verify mode Program inhibit mode +12.5V +6V PA-17KDZ PA-17P709GC To PG-1500 |
Similar Part No. - UPD17P709 |
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Similar Description - UPD17P709 |
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