TQM879006A

1.4 −2.7 GHz ¼ W Digital Variable Amplifier

Datasheet: Rev R 11-15-13

- 6 of 11 -

Disclaimer: Subject to change without notice

© 2013 TriQuint

www.triquint.com

Serial Control Interface Timing Diagram

CLK is disabled when LE is high

SERIN

CLK

LE

D5-D0

MSB-LSB

D5-D0

MSB-LSB

Serial Control Interface

CC

Parameter

Condition

Min

Max

Units

Clock Frequency

50% Duty Cycle

10

MHz

after last CLK rising edge

10

ns

30

ns

before CLK rising edge

10

ns

after CLK rising edge

10

ns

LE to LE pulse spacing

630

ns

LE to Parallel output valid

30

ns

CC

Parameter

Condition

Min

Max

Units

0

0.8

V

2.4

Vcc

V

On DATA, LE and CLK

-10

+10

µA

DATA (MSB in First 6-Bit Word) Control Logic Truth Table

MSB

6-Bit Control Word to DSA

LSB

Gain Relative to Maximum Gain

D5

D4

D3

D2

D1

D0

Reference : IL

1

1

1

1

1

1

0 dB

1

1

1

1

1

0

0.5 dB

1

1

1

1

0

1

1 dB

1

1

1

0

1

1

2 dB

1

1

0

1

1

1

4 dB

1

0

1

1

1

1

8 dB

0

1

1

1

1

1

16 dB

0

0

0

0

0

0

31.5 dB

Any combination of the possible 64 states will provide a reduction in gain of approximately the sum of the bits selected.

DATA