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UPD17145 Datasheet(PDF) 51 Page - NEC |
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UPD17145 Datasheet(HTML) 51 Page - NEC |
51 / 102 page 51 µPD17145(A1), 17147(A1), 17149(A1) Figure 15-1. Block Diagram of Serial Interface Caution The output latch of the shift register is independent of the output latch of P0D1. Therefore, even if an output instruction is executed to P0D1, the status of the output latch of the shift register is not affected. The output latch of the shift register is cleared to “0” by RESET input. After that, it holds the status of the LSB of the previously transferred data. P0D2/SI P0D1/SO P0D0/SCK Shift register (SIOSFR) P0D1 output latch Serial clock counter Clear Selector SIOTS SIOHIZ SIOCK1 SIOCK0 IRQSIO clear signal IRQSIO set signal One shot SIOEN P0DBIO0 P0DBIO1 Q S R Output latch LSB MSB Clock Carry P0D0 output latch |
Similar Part No. - UPD17145 |
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Similar Description - UPD17145 |
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