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UPD17145 Datasheet(PDF) 30 Page - NEC |
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UPD17145 Datasheet(HTML) 30 Page - NEC |
30 / 102 page 30 µPD17145(A1), 17147(A1), 17149(A1) 11. PORTS 11.1 Port 0A (P0A0, P0A1, P0A2, P0A3) Port 0A is a 4-bit I/O port with an output latch. It is mapped at address 70H of BANK0 of the data memory. The output format is CMOS push-pull output. This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0AGIO (bit 0 of address 2CH) on the register file. When P0AGIO = 0, all the pins of port 0A are set in the input mode. When an instruction that reads the data of the port register is executed at this time, the pin status is read. When P0AGIO = 1, all the pins of port 0A are set in the output mode, and the contents written to the output latch are output to the pins. When an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is connected is specified by P0AGPU (bit 0 at address 0CH) of the register file. All the four pins are pulled up when P0AGPU = 1. When P0AGPU = 0, the pull-up resistor is not connected. P0AGIO and P0AGPU are cleared to “0” at reset, and all the P0A pins are set in the input mode without the pull-up resistor connected. The value of the output latch is also cleared to “0”. Table 11-1. Writing and Reading Port Register (0.70H) P0AGIO Input/Output BANK0 70H RF: 2CH, bit 0 Mode of Pin Write Read 0 Input Enabled P0A pin status 1 Output Write to P0A latch P0A latch contents |
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