UPD17072 datasheet(90/226 Pages) NEC

Part #	UPD17072

Description	4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM

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Manufacturer	NEC [NEC]

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µPD17072,17073

90

(4) If detection of BTM0CY flag overlaps with CE reset

As described in (3), the CE reset is effected as soon as the BTM0CY flag has been set to 1.

If the BTM0CY flag read instruction happens to be executed at the same time as the CE reset, the BTM0CY

flag read instruction takes precedence.

Therefore, if setting of the BTM0CY flag after the CE pin has gone high overlaps with the BTM0CY flag read

instruction, the CE reset is effected when “the BTM0CY flag is set next time”.

This operation is illustrated in Figure 12-6.

Figure 12-6. Operation when CE Reset and BTM0CY Flag Read Instruction Overlap

In a program that cyclically detects the BTM0CY flag, in which the BTM0CY flag detection time interval

coincides with the BTM0CY flag setting time, CE reset is never effected.

H

L

H

L

1

0

CE pin

BTM0CY flag

setting pulse

BTM0CY flag

SKT 1

BTM0CY

SKT 1

BTM0CY

CE reset

H

L

1

0

BTM0CY flag

setting pulse

BTM0CY flag

Instruction

SKT1 BTM0CY

53.3 s

µ

Embedded macro

SKT .MF. BTM0CY SHR4,

#.DF. BTM0CY AND 0FH

If BTM0CY flag is read during

this period, CE is delayed.

Originally, program starts from address 0000H here.

However, because it happens to overlap with a

program that reads BTM0CY, CE reset is not effected.

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