TAT8804D1H

21 dB CATV 12V Power Doubler

Pin Configuration and Description

Amp

LIN

6

7

8

9

10

11

12

1

2

3

4

5

BIAS

37

35

36

33

34

40

38

39

16

18

17

20

19

13

15

14

27

26

25

24

23

22

21

32

31

30

29

28

BIAS

RFin A

RFin B

GND

CS

I

V

DD

V

DD

V

DD

V

DD

RFOut A

V

DD

RFOut B

V

DD

GND

GND

N/C

GND

GND

GND

GND

GND

GND

GND

GND

Exposed Backside Pad (EP) - GND

Pin 1 Marking

Pin No.

Label

Description

2-4

RFin A

RF in A, requires external Balun. External DC Block required.

9-11

RFin B

RF in B, requires external Balun. External DC Block required.

5

ILIN

Current adjust pin to optimize Linearity

28-29

RF Out A and supply voltage, external DC block & Balun required.

24-25

RF Out B and supply voltage, external DC block & Balun required.

18-19, 34-35

Bias controller supply voltage

27

Common Gate adjustment to optimize common gate amplifier bias voltage

(normally open)

38

1,8,12-17, 20-21, 26,

32-33, 36-37, 39-40

GND

RF/DC Ground Connection

6-7

Common Source ground degeneration, grounded with inductor. Full DC

Backside Paddle

GND

RF/DC ground. Use recommended via pattern to minimize inductance and

thermal resistance. See PCB Mounting Pattern for suggested footprint.

22-23, 30-31, 39

N/C

No connection

Evaluation Board PCB Information

EB & EBP EVB PCB Material and Stack-up

Board Material: 0.062" FR4 ,

ε

r

=4.25

Plating: 2oz Copper

Board Dimension: 3" x 2"

2 oz Copper

FR4

2 oz Copper

0.062"

0.0014"

0.0014"

C9

R3

C10

C3

C4

R1

L4

L3

T2

T1

J1

J2

U1

L6

J3

L2

C19

Datasheet: Rev I 06-23-14

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Disclaimer: Subject to change without notice

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www.triquint.com