AH323

2W High Linearity 5V 2-Stage Amplifier

Datasheet: Rev G 06-22-14

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Disclaimer: Subject to change without notice

© 2014 TriQuint

www.triquint.com

Reference Design 1800-1900 MHz

Notes:

1. See PC Board Layout, page 15 for more information.

2. Vcc1 is connected to Vcc2_bias J3 turret via inner layer line.

3. The primary RF microstrip characteristic line impedance is 50 Ω.

4. Components shown on the silkscreen but not on the schematic are not used.

5. The edge of C2 is placed at 128 mils from the U1 device package (12.5° @ 1850 MHz).

6. The edge of C3 is placed at 70 mils from the edge of U1 device package (7° @ 1850 MHz).

7. The edge of C13 is placed at 110 mils from the edge of U1 device package (10.7° @ 1850 MHz).

8. Zero ohm jumpers may be replaced with copper traces in the target application layout.

9. The locations of C6 and C15 are non-critical. They can be placed closer to the device. C6 can be replaced by 0 ohm jumper.

10. Ferrite Bead FB1 eliminates bias line resonances between C10 and the parasitic inductance of C11. Steward MI0603K300R-10.

Typical Performance 1800-1900 MHz

Test conditions unless otherwise noted:

Parameter

Conditions

Units

Frequency

1800

1850

1900

MHz

Gain

28.6

28.8

28.6

dB

Input Return Loss

13

17.6

20.5

dB

Output Return Loss

10.5

13

14.4

dB

Output P1dB

+33.2

+33.3

+33.1

dBm

OIP3

Pout = +24 dBm/tone, ∆f = 1 MHz

+49

+50

+49

dBm

ACLR = -50 dBc

+23.7

+23.9

+23.9

dBm

Notes:

1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5MHz offset, PAR = 9.6 dB @ 0.01% Prob.

See Notes for Matching

Component Locations.