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S13158EJ4V0DS00 Datasheet(PDF) 7 Page - Renesas Technology Corp |
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S13158EJ4V0DS00 Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 22 page Data Sheet S13158EJ4V0DS 5 µ PD3737 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2 −0.3 to +8 V Last stage shift register clock voltage Vφ 1L, Vφ 2L −0.3 to +8 V Reset signal voltage Vφ R −0.3 to +8 V Transfer gate clock voltage Vφ TG −0.3 to +8 V Operating ambient temperature Note TA 0 to +60 °C Storage temperature Tstg −40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol Min. Typ. Max. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ 1_H, Vφ 2_H 4.5 5.0 5.5 V Shift register clock low level Vφ 1_L, Vφ 2_L −0.3 0 +0.5 V Last stage shift register clock high level Vφ 1LH, Vφ 2LH 4.5 5.0 5.5 V Last stage shift register clock low level Vφ 1LL, Vφ 2LL −0.3 0 +0.5 V Reset signal φR high level Vφ RH 4.5 5.0 5.5 V Reset signal φR low level Vφ RL −0.3 0 +0.5 V Transfer gate clock high level Vφ TGH 4.5 Vφ 1_H Note Vφ 1_H Note V Transfer gate clock low level Vφ TGL −0.3 0 +0.5 V Shift register clock amplitude Vφ 1_pp, Vφ 2_pp 4.5 5.0 5.8 V Last stage shift register clock amplitude Vφ 1L_pp, Vφ 2L_pp 4.5 5.0 5.8 V Reset signal amplitude Vφ R_pp 4.5 5.0 5.8 V Transfer gate clock amplitude Vφ TG_pp 4.5 5.0 5.8 V Data rate fφ R 0.5 1 20 MHz Note When Transfer gate clock high level (Vφ TGH) is higher than Shift register clock high level (Vφ 1_H), Image lag can increase. Remarks1. Input reset signal φ R to pin 32 via capacitor (1000 pF ±20%, non polarity). Concerning the connection method refer to APPLICATION CIRCUIT EXAMPLE. 2. Operating conditions of reset signal φ R is not the condition at device pins but the conditions of the signal which applied to capacitor. |
Similar Part No. - S13158EJ4V0DS00_15 |
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Similar Description - S13158EJ4V0DS00_15 |
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