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PD44164182B Datasheet(PDF) 8 Page - Renesas Technology Corp |
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PD44164182B Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 35 page μPD44164182B, μPD44164362B R10DS0014EJ0200 Rev.2.00 Page 8 of 34 October 6, 2011 Power-On Sequence in DDR II SRAM DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. The following timing charts show the recommended power-on sequence. The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down. Power-On Sequence Apply power and tie DLL# to HIGH. - Apply VDD before VDDQ. - Apply VDDQ before VREF or at the same time as VREF. Provide stable clock for more than 20 μs to lock the PLL. PLL Constraints The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an undesired clock frequency. Power-On Waveforms DLL# 20 μs or more Stable Clock VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Fix HIGH (or tied to VDDQ) VDD/VDDQ Clock Unstable Clock Normal Operation Start |
Similar Part No. - PD44164182B_15 |
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Similar Description - PD44164182B_15 |
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