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UPD16772A Datasheet(PDF) 5 Page - NEC |
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UPD16772A Datasheet(HTML) 5 Page - NEC |
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Data Sheet S14725EJ1V0DS00 5 µµµµPD16772A Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V9 is possible.). 2. To stabilize the supply voltage, please be sure to insert a 0.1 µµµµF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µµµµF is also advised between the γγγγ -corrected power supply terminals (V0, V1, V2,....., V9) and VSS2. |
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