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NP100N04NUJ Datasheet(PDF) 2 Page - Renesas Technology Corp |
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NP100N04NUJ Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 8 page 
NP100N04NUJ Chapter Title R07DS0364EJ0100 Rev.1.00 Page 2 of 6 Jun 13, 2011 Electrical Characteristics (TA = 25 °C) Item Symbol MIN. TYP. MAX. Unit Test Conditions Zero Gate Voltage Drain Current IDSS 1.0 μA VDS = 40 V, VGS = 0 V Gate Leakage Current IGSS ±100 nA VGS = ±20 V, VDS = 0 V Gate to Source Threshold Voltage VGS(th) 2.0 3.0 4.0 V VDS = VGS, ID = 250 μ A Forward Transfer Admittance ∗ 1 | yfs | 45 87 S VDS = 5 V, ID = 50 A Drain to Source On-state Resistance ∗ 1 RDS(on) 2.5 3.0 m Ω VGS = 10 V, ID = 50 A Input Capacitance Ciss 5600 8400 pF VDS = 25 V, Output Capacitance Coss 920 1380 pF VGS = 0 V, Reverse Transfer Capacitance Crss 340 620 pF f = 1 MHz Turn-on Delay Time td(on) 25 60 ns VDD = 20 V, ID = 50 A, Rise Time tr 15 40 ns VGS = 10 V, Turn-off Delay Time td(off) 93 190 ns RG = 0 Ω Fall Time tf 13 40 ns Total Gate Charge QG 110 170 nC Gate to Source Charge QGS 22 nC Gate to Drain Charge QGD 32 nC VDD = 32 V, VGS = 10 V, ID = 100 A Body Diode Forward Voltage ∗ 1 VF(S-D) 0.9 1.5 V IF = 100 A, VGS = 0 V Reverse Recovery Time trr 55 ns Reverse Recovery Charge Qrr 77 nC IF = 100 A, VGS = 0 V, di/dt = 100 A/ μ s Note: ∗1. Pulsed test TEST CIRCUIT 3 GATE CHARGE VGS = 20 → 0 V PG. RG = 25 Ω 50 Ω D.U.T. L VDD TEST CIRCUIT 1 AVALANCHE CAPABILITY PG. D.U.T. RL VDD TEST CIRCUIT 2 SWITCHING TIME RG PG. IG = 2 mA 50 Ω D.U.T. RL VDD ID VDD IAS VDS BVDSS Starting Tch VGS 0 = 1 s Duty Cycle ≤ 1% τ μ τ VGS Wave Form VDS Wave Form VGS VDS 10% 0 0 90% 90% 90% VGS VDS ton toff td(on) tr td(off) tf 10% 10% |
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