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R5F2136ASDFP Datasheet(PDF) 2 Page - Renesas Technology Corp |
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R5F2136ASDFP Datasheet(HTML) 2 Page - Renesas Technology Corp |
2 / 61 page R8C/36T-A Group 1. Overview R01DS0055EJ0100 Rev.1.00 Page 2 of 58 Dec 09, 2011 1.1.2 Specifications Tables 1.1 and 1.2 outline Specifications. Table 1.1 Specifications (1) Item Function Description CPU Central processing unit R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (CPU clock = 20 MHz, VCC = 2.7 V to 5.5 V) 200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 5.5 V) • Multiplier: 16 bits × 16 bits 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Memory ROM, RAM, data flash Refer to Table 1.3 Product List. Voltage detection Voltage detection circuit • Power-on reset • Voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) I/O ports Programmable I/O ports • Input only: 1 • CMOS I/O: 59, selectable pull-up resistor • High current drive ports: 59 Clock Clock generation circuits • 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit, high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected • Low-power mode: Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Interrupts • Number of interrupt vectors: 69 • External interrupt inputs: 9 (INT × 5, key input × 4) • Priority levels: 7 Event link controller (ELC) • Events output from peripheral functions can be linked to events input to different peripheral functions. (30 sources × 10 types of event link operations) • Events can be handled independently from interrupt requests. Watchdog timer • 14 bits × 1 • Selectable reset start function • Selectable low-speed on-chip oscillator for the watchdog timer DTC (data transfer controller) • 1 channel • Activation sources: 27 • Transfer modes: 2 (normal mode, repeat mode) Timer Timers RJ_0 16 bits × 1: 1 circuit integrated on-chip Timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode Timer RB2_0 16 bits × 1: 1 circuit integrated on-chip Timer mode (periodic timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one-shot generation mode Timers RC_0 16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip Timer mode (input capture function, output compare function), PWM mode (output: 3 pins), PWM2 mode (PWM output: 1 pin) Timer RE2 8 bits × 1 Compare match timer mode, real-time clock mode |
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