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CDCL1810ARGZT Datasheet(PDF) 1 Page - Texas Instruments

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Part # CDCL1810ARGZT
Description  Single 1.8 V Supply
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCL1810ARGZT Datasheet(HTML) 1 Page - Texas Instruments

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SDA/SCL
Differential
LVDSInput
Upto650MHz
5Differential
CMLOutputs
Upto650MHz
5Differential
CMLOutputs
Upto650MHz
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CDCL1810A
SLLSEL1 – NOVEMBER 2014
CDCL1810A 1.8V, 10 Output, High-Performance Clock Distributor
1 Features
3 Description
The
CDCL1810A
is
a
high-performance
clock
1
Single 1.8 V Supply
distributor. The programmable dividers, P0 and P1,
High-Performance Clock Distributor with 10
give a high flexibility to the ratio of the output
Outputs
frequency to the input frequency: FOUT = FIN/P, where
Low Input-to-Output Additive Jitter: as low as 10fs
P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.
RMS
The CDCL1810A supports one differential LVDS
Low-Voltage Differential Signaling (LVDS) Input,
clock input and a total of 10 differential CML outputs.
100
Ω Differential On-Chip Termination, up to 650
The CML outputs are compatible with LVDS receivers
MHz Frequency
if they are ac-coupled.
Differential Current Mode Logic (CML) Outputs,
With careful observation of the input voltage swing
50
Ω Single-Ended On-Chip Termination, up to
and common-mode voltage limits, the CDCL1810A
650 MHz Frequency
can support a single-ended clock input as outlined in
Pin Configuration and Functions.
Two Groups of Five Outputs Each with
Independent Frequency Division Ratios
All device settings are programmable through the
SDA/SCL,
serial
two-wire
interface.
The
serial
Output Frequency Derived with Divide Ratios of 1,
interface is 1.8V tolerant only.
2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
Meets ANSI TIA/EIA-644-A-2001 LVDS Standard
The device operates in a 1.8V supply environment
Requirements
and is characterized for operation from –40°C to
+85°C. The CDCL1810A is available in a 48-pin QFN
Power Consumption: 410 mW Typical
(RGZ) package.
Output Enable Control for Each Output
SDA/SCL Device Management Interface
Device Information(1)
48-pin VQFN (RGZ) Package
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCL1810A
VQFN (48)
7.00 mm × 7.00 mm
Industrial Temperature Range: –40°C to +85°C
(1) For all available packages, see the orderable addendum at
2 Applications
the end of the datasheet.
Clock Distribution for High-Speed SERDES
Distribution of SERDES Reference Clocks for
1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel,
PCI Express, Serial ATA, SONET, CPRI, OBSAI,
and so forth
Up to 1-to-10 Clock Buffering and Fan-out
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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