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CDCL1810ARGZT Datasheet(PDF) 8 Page - Texas Instruments |
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CDCL1810ARGZT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 30 page ![]() CDCL1810A SLLSEL1 – NOVEMBER 2014 www.ti.com AC Electrical Characteristics (continued) Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADDITIVE CLOCK OUTPUT JITTER 10 Hz to 1 MHz offset 180 FIN = 30.72MHz, FOUT = 30.72MHz 1 MHz to 5 MHz offset 348 fs RMS VD,IN = 200mVPP 12 kHz to 5 MHz offset 388 10 Hz to 1 MHz offset 175 FIN = 30.72MHz, FOUT = 30.72MHz 1 MHz to 5 MHz offset 347 fs RMS VD,IN = 1200mVPP 12 kHz to 5 MHz offset 388 JOUT 10 Hz to 1 MHz offset 41 FIN = 650MHz, FOUT = 650MHz 1 MHz to 20 MHz offset 36 fs RMS VD,IN = 200mVPP 12 kHz to 20 MHz offset 42 10 Hz to 1 MHz offset 48 FIN = 650MHz, FOUT = 650MHz 1 MHz to 20 MHz offset 33 fs RMS VD,IN = 1200mVPP 12 kHz to 20 MHz offset 39 FIN = 30.72MHz, TP Input-to-output delay FOUT = 30.72MHz 0.7 ns YP[9:0] outputs FIN = 30.72MHz, FOUT = 30.72MHz TSOUT Clock output skew –64 64 ps YP[9:0] outputs relative to YP[0] 8.7 AC Electrical Characteristics for the SDA/SCL Interface (1) PARAMETER MIN TYP MAX UNIT fSCL SCL frequency 400 kHz th(START) START hold time 0.6 μs tw(SCLL) SCL low-pulse duration 1.3 μs tw(SCLH) SCL high-pulse duration 0.6 μs tsu(START) START setup time 0.6 μs th(SDATA) SDA hold time 0 μs tsu(DATA) SDA setup time 0.6 μs tr(SDATA) SCL / SDA input rise time 0.3 μs tf(SDATA) SCL / SDA input fall time 0.3 μs tsu(STOP) STOP setup time 0.6 μs tBUS bus free time 1.3 μs (1) See Figure 7 for the timing behavior. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CDCL1810A |
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