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R5F213J4TNNP Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R5F213J4TNNP Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 50 page R01DS0045EJ0100 Rev.1.00 Page 5 of 47 Apr 26, 2011 R8C/3JT Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a Block Diagram. Figure 1.2 Block Diagram R8C CPU core Memory ROM (1) RAM (2) Multiplier R0H R0L R1H R2 R3 R1L A0 A1 FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. 8 Port P1 5 Port P3 3 1 Port P4 8 Port P0 7 Port P2 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Watchdog timer (14 bits) A/D converter (10 bits × 12 channels) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator Voltage detection circuit DTC Low-speed on-chip oscillator for watchdog timer UART or clock synchronous serial I/O (8 bits × 2) LIN module Sensor Control Unit |
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